In a 3D logic-on-logic configuration, the top logic die must be powered with current coming directly from the substrate. Depending on the particular device, a current delivery requirement may be 300 milliamps (mA) to 350 mA per controlled-collapse chip connection (C4) or copper pillar (CuP) connection on the bottom die of the 3D IC stack. The required current must be transferred directly to the top die, which cannot be done through a single TSV. In addition, there is the problem of the current spreading throughout the top die because of “bottlenecking” due to the micropillar connections of the top die, e.g., a max current load for each micropillar is approximately 65 mA.
A need therefore exists for methodology enabling full current flow from a bottom die C4/CuP connection to the top die of a 3D IC stack and a uniform power/ground distribution network and the resulting device.